This project integrates research and education in the design of memory hierarchies. The research augments conventional cache management techniques with more sophisticated reference history information. These techniques include programmer-supplied annotations, hardware buffers to identify and exploit locality, use of latency tolerance to decide on invalidation of cache lines, and prefetching of thread working sets. These research efforts will be integrated into the undergraduate and graduate curriculum by adding courses, organizing a working group on computer architecture, and maintaining a web site on memory hierarchy management.
