This project involves development of a new reconfigurable computing architecture, called MorphoSys, through close collaboration among researchers and students at University of California, Irvine (UCI) and the Federal University of Rio de Janeiro (UFRJ). This unique architecture combines a reconfigurable Single Instruction Multiple Data (SIMD) coprocessor with a RISC core microprocessor on the same chip. Moreover, in order to address the special needs of image/signal processing applications, the MorphoSys architecture includes a unique image data buffer for efficient data streaming. Behavioral level simulation of the M1 chip has shown the architecture to be quite promising for a variety of applications (MPEG-2 and ATR), achieving performance much more superior to the standard general purpose microprocessors and close to specialized ASIC-based solutions.
The UCI and UFRJ researchers have been working closely for the development of the behavioral model of M1 chip. The UFRJ research group has designed the RISC core that is used for controlling the SIMD coprocessor in M1. This block is considered one of the most complex components of the chip requiring custom-made as well as synthesizable circuits. It is proposed that UFRJ group handle the physical design of the RISC core, while the UCI group completes the remaining blocks of the M1 chip that is estimated to have more than 1.5 million transistors.
Along with physical design, the other objectives for collaboration between the two groups at UCI and UFRJ include development of programming and testing environment for M1, mapping and performance evaluation for a wide range of applications, and design of second version of the MorphoSys architecture. We visualize that this collaboration will enhance the educational experience of students both at UCI and at UFRJ in Brazil, by providing them an opportunity to work in a competitive, target-oriented, multi-cultural environment using the latest technology.
