Emerging nanodevices, such as carbon nanotubes, have been recognized as very promising for future technology scaling. A recent innovation has enabled the fabrication of nanotube-based non-volatile random-access memory (NRAM) that has the promise to become a universal memory. NRAMs are suitable for both standalone and embedded memory applications and are fabricated using traditional lithography-compatible manufacturing processes. An NRAM is considerably faster and denser than DRAM, has much lower power consumption than DRAM or flash, has similar speed to SRAM and is highly resistant to environmental forces (temperature, magnetism).
The aim of this project is to explore an NRAM-based class of programmable computer architectures, known as a field-programmable gate array (FPGA) family. Initial work in the PI's group on such FPGAs has shown the feasibility of increasing the logic density by over an order of magnitude compared to traditional FPGAs, using the novel concept of fine-grain temporal logic folding, which makes cycle-by-cycle dynamic reconfiguration feasible.
The objectives of this project include design space exploration of the NRAM-based FPGA space using a parameterized technology mapping and temporal logic folding tool that takes a mixed register-transfer/gate level description of a circuit and maps it to an NRAM-based FPGA family instance. The research will also explore the applicability of such FPGAs to computation-unit integrated memories for memory-intensive multimedia applications.
The proposed work will make a well-characterized and highly versatile family of NRAM-based FPGAs and associated mapper/folder available to industry. The material will be included in a new senior-level course on Design with Nanotechnologies. Undergraduate students are expected to participate in this research. Female and minority students will be attracted to this research through Princeton's Presidential Fellowship Program.
