The objective of this research is to investigate innovative frequency channelized architectures for broadband analog-to-digital conversion. The approach employs a broadband analog iterative filter bank based on a spatially unfolded cascade of image-reject down-conversion stages. For an N-stage cascade, the input is concurrently decomposed into 2 to the power of N-1 contiguous channels; each digitized using converters clocked at 1/(2 to the power of N-1) of the input Nyquist rate. All down converter local oscillators are derived from a single reference with a cascade of compact, low power, divide-by-2 stages. The architecture potentially allows for frequency scalable resolution.
Intellectual Merit: The approach in this research does not suffer from limitations of traditional high-speed time-domain samplers, such as requirements for extremely fine time resolution. It also avoids a major implementation bottleneck in current frequency-domain approaches arising from the requirement for multiple non-harmonically related local oscillators. Performance limitations due to finite image-rejection, local oscillator spurs, and phase noise are addressed with circuit-level innovations.
Broader Impacts: The innovations in signal digitization capability address a critical need for technology advances in multiple areas with broad societal and scientific impact including computing, communications, sensors, medicine, and fundamental science. The unique architecture is expected to enable new signal-processing intensive implementations utilizing multi-resolution and frequency scalable designs with diverse applications in these areas. Graduate and undergraduate students involved in this research will gain expertise in theoretical and experimental aspects of the design of high-performance digitizers and signal processors. The results of this research will be disseminated through publications and seminars and will be incorporated into graduate courses taught by the PIs.
The ability to digitize signals is fundamental to advances in many areas with societal and scientific impact such as communications, computing, medicine and tools for scientific research. In recent decades, the availability of scaled nanometer technologies has made digital-centric hardware for such applications cost-effective and robust. Furthermore, through the use of digital signal processing techniques it is possible to achieve excellent performance and programmability in such implementations. While digital-centric architectures are desirable, signals in the real world are often analog in nature, and are characterized by a continuously varying amplitude as a function of time. Thus in several systems, the input signal needs to be converted from the analog domain to a digital representation, which is accomplished by means of a circuit block termed an analog-to-digital converter (ADC). The ADC samples the input signal using a periodic clock and then approximates the sampled continuous-amplitude signal by a discrete amplitude. Two key characteristics of an analog signal that determine the performance requirement of the ADC include the range of variation of its amplitude, and the rate at which the amplitude varies. The first characteristic determines the dynamic range of the signal, while the second determines the frequency span or the bandwidth of the signal. A signal with faster variation has a wider bandwidth in the frequency domain. A major challenge in analog-to-digital converter designs arises as the bandwidth of the analog signal starts approaching the performance limits of the devices available in the process technology. Typically this leads to a deterioration in performance, or a significant increase in power dissipation in order to maintain the performance level. As part of this research, the above limitation in ADC designs was addressed using architectures that decompose a broadband analog signal into multiple frequency sub-bands. In the proposed approaches, sub-bands within the input spectrum are downconverted to baseband in mixers that multiply the input signal with a local oscillator signal (LO) provided by a frequency synthesizer. ADCs can be used to digitize the analog signal in each of the sub-bands. The ADC bandwidth requirement per sub-band is relaxed compared to full-band digitization. In traditional frequency-domain ADCs each downconversion mixer utilizes a distinct frequency synthesizer in order to translate the associated sub-band to baseband. This approach requires multiple synthesizers in a single integrated circuit, which can cause serious challenges for instance due to coupling of signals from one synthesizer to another. Furthermore harmonics of the LO signal generated within the mixer can cause unintended parts of the input spectrum to be downconverted to baseband. In order to reduce the LO harmonic content, a special type of downconversion mixer termed a harmonic rejection mixer (HRM) has been investigated and implemented in a 130 nm CMOS process as part of the research. The design is demonstrated to provide a rejection of undesired harmonics by greater than 60 dB, or a linear factor of 1000, in the presence of device variations without calibration or filtering, and represents state-of-the-art performance. The design operates up to a bandwidth of 830 MHz. This HRM is also capable of internally synthesizing multiple programmable LO signals, while using a single high-frequency primary clock. Multiple such HRMs, all using the same high frequency clock but programmed to provide different effective LO signals can be used in parallel to implement a frequency-domain analog-to-digital converter. A mixed-signal frequency-folded ADC architecture has also been proposed and implemented in a 65nm CMOS process. The design differs from the above in that distinct portions of the input spectrum are folded down to a fixed baseband frequency in multiple paths. The multiple paths use non-overlapping rectangular clock pulses of a specific duty cycle and a single frequency, with all clocks being offset relative to each other. The baseband signals which contain all sub-bands are first digitized in sub-band ADCs. Harmonic rejection is implemented in the digital domain. This design operates up to an analog bandwidth of 1 GHz. Image and harmonic rejection are calibrated in the digital domain. This design is well-suited for applications where full spectrum digitization is required. The design of HRMs up to 8 GHz signal bandwidth has also been investigated as part of the work. The above architectures solve fundamental limitations with frequency-domain ADCs, and thus open the door to new architectures and implementations for a wide range of applications, such as spectrum analysis, wireless communications, including software defined radio and cognitive radio, cable tuner architectures, and mixed-signal processors. This work has contributed directly to the doctoral research of two students. The research has been reported in two journal publications, and a conference paper. The research topics have motivated classroom assignments, projects and teaching modules in the graduate-level Radio Frequency Integrated Circuits class taught by the PI at the University of Texas at Austin.
