The objective of this project is to lay the groundwork for completely re-thinking Network-on-Chips (NoCs) design and propose to exploit the unique advantages of the emerging interconnect technologies such as photonics and wireless for designing performance scalable, and power-efficient NoCs for future multicores.
Intellectual Merits:
Power consumed by digital devices and systems such as smartphones, laptops, servers and datacenters is increasing at an alarming rate as more computing cores can be integrated on a single chip. The computing capabilities of multicore architectures can be unleashed only if the underlying network that transports data between the cores and the caches can provide scalable bandwidth at low power consumption. Research has shown that disruptive technology solutions such as photonics and wireless technologies have the potential to alleviate the critical bandwidth, power, and latency challenges of future multicore architectures. The proposed research combines multiple interconnect technologies to achieve three objectives, namely: (1) scalability to 1000 cores, (2) power efficiency (at least a 50% reduction as compared to state-of-the art metallic interconnects), and (3) high bandwidth and low latency across a wide variety of applications.
Broader Impacts:
The proposed research has the potential to transform the design of next-generation NoCs and multicore architectures, which are essential for the continued growth of computing performance. This proposal describes a transformative and viable approach that integrates research in technology, architecture, algorithm and applications for designing energy-efficient NoCs thus enabling scalable multicore architectures. The research will also play a major role in education by integrating discovery with teaching and training. Finally, the results and findings of the proposed research will be disseminated to researchers, engineers and educators through technical publications and presentations.
