The objective of this proposal is to develop a new noise-aware design methodology that can maximize the error resilience of signal processing integrated circuits. As CMOS technology approaches its end-of-roadmap physical limit, there have been increasing levels of environmental and process variations, and susceptibility to noise, which make it a challenge to maintain the historical yield and reliability. This proposal will develop methodology and approaches that tackle this grand challenge in the context of signal processing integrated circuits implementation. The intellectual merit of this proposal lies in the research theme of leveraging the unique characteristics of signal processing functions to substantially improve the tolerance to noise. There are two major parts to this project: developing noise analysis techniques for signal processing integrated circuits, and exploring design space for noise-aware VLSI signal processing. In particular, this research will develop analysis techniques that can quantitatively estimate how variations in signal processing integrated circuits may affect the signal processing performance. This research will further explore the design space for noise-aware VLSI signal processing where the objective is to minimize the noise-induced signal processing performance degradation at minimal energy consumption and/or silicon cost.
The proposed research program represents the first step towards exploring a new research area. If successful, it will have broad impact on the semiconductor industry and national economy in both the near term and long term: In the near term, it will generate considerable economic benefit by improving the noise tolerance and the effective yield of signal processing integrated circuits. From another perspective, it will enable more aggressive CMOS scaling for implementing signal processing integrated circuits, which will be greatly beneficial since the signal processing functions are typically very hardware resource demanding. In the long term, this research will shed light on signal processing system implementation using post-silicon nanotechnology, such as molecular electronics, where a significant degree of noise is presumably inevitable. The education objective of this proposal is to promote the education of VLSI signal processing, the inter-disciplinary area linking semiconductor and signal processing/communication, to a wider spectrum of students.
The objective of this sponsored research project is to develop new design methodologies that can enable future signal processing integrated systems exploit the semiconductor technology scaling to its full extent. As semiconductor technology approaches its end-of-roadmap physical limit, there have been increasing levels of environmental and process variations, and susceptibility to noise, which make it a challenge to maintain the historical yield and reliability. This research projects develop several new design techniques that cohesively exploit the features of digital single processing algorithms and hardware architectures to maximize the signal processing circuits immunity and tolerance to less-reliable semiconductor technology. The major research accomplishments include: (1) Development of a computation error analysis method for digital signal processing systems with overscaled supply voltage. In most signal processing systems, various computer arithmetic functions, particularly addition and multiplication, are major building blocks and typically constitute the critical paths. Therefore, signal processing performance degradation incurred by voltage overscaling heavily depends on the output transient error characteristics of those computer arithmetic functions in response to overscaled supply voltage. We developed an analytical method that can estimate the average magnitude of computation errors of voltage overscaled computer arithmetics, which is critical for designers to architect voltage overscaled signal processing systems. (2) Development of techniques to design voltage overscaled low-power trellis decoders in the presence of process variations. Trellis decoders are pervasive in digital communication and data storage for realizing forward error correction and signal detection. Leveraging the fact that most signal processing functions mainly concern certain quantitative performance criteria, such as bit error rate and signal to noise ratio (SNR), we developed a solution to design voltage overscaled trellis decoders, which can largely improve the tolerance to technology process variation. (3) Development of an adaptive finite word-length configuration design methodology for low-power variation tolerant signal processing systems. We investigated the use of adaptive finite word-length configuration in digital signal processing integrated circuits for improving system-level tolerance to process variations. We developed a design flow that can be used to help designers search for the entire design space and identify the optimal solution. (4) Development of a heterogeneous and reconfigurable signal processing system design framework. We developed a class of heterogeneous multiprocessor architectures, which is called field programmable X arrays, (FPXAs). Like FPGAs, FPXAs can be viewed as arrays of configurable processing elements; however, in FPXAs the elements themselves can be arbitrary (typically coarse-grain) structures. Such heterogeneous reconfigurable architecture can naturally match to the compute-intensive and data-streaming characteristics of signal processing functions, and bring several attractive features, including (i) it can run-time provide just-enough computation and storage resource for the present signal processing tasks, hence can achieve a high energy efficiency; (ii) the architectural reconfigurability can be seamlessly exploited to improve the immunity to underlying circuit noises in future extremely scaled technology nodes.
