Today, practically all processors employ instruction set architectures which are functionally equivalent to each other. Compiler/micro-architecture cooperation using these traditional representations has already reached the point of diminishing returns. This project therefore investigates the domain of single assignment program representations and direct support of this domain through micro-architecture implementation as a key concept that can break the barriers between the compilers and architectures. If successful, this new approach can have a significant impact on the design of future processors, design of compiler internal representations as well as the back-end of the compilers. It can also affect how parallelism is exploited at various granularities and how various optimizations are carried out. The investigated framework can help revitalize computer architecture and compiler optimization research by opening up unexplored paths for research in high-performance systems. Consequently, it can affect every field of science and commerce which rely on high-performance computation.
Compiler/hardware integration around the concept of single-assignment form has many benefits spanning three fields. First, in the area of process synchronization it provides the opportunity to eliminate the need for explicit synchronization. Second, in the field of micro-architecture renaming of instruction streams becomes substantially simpler, micro-architectures can become loop-aware, renamed instruction streams can be re-renamed and compiler techniques such as partial redundancy elimination or constant propagation can dynamically be performed by the micro-architecture. Finally, the compilers can focus on what they do best by sharing a common representation with the micro-architecture. As a result, many key optimizations can be efficiently performed. Within this paradigm, it becomes possible to develop new optimization algorithms which will rely on the micro-architecture to perform the optimization using analysis performed by the compilers.