This research is on accelerating mixed level simulation using general purpose parallel processors. An existing parallel simulator is being developed to make the code more portable and available for others to use on several parallel machines. Parallel discrete event simulation is being used. Topics addressed are: (1) finding techniques for improving the simulation of large fan- out circuit nodes; and (2) developing graph manipulation algorithms to improve partitioning, to improve signal distribution, and to do asynchronous message passing. Experiments on benchmark designs with the simulator to study the effects of partitioning, component migration, task size, and computational and communication overhead are being conducted.
