This project involves the development of new fault models and on-chip test methods for large embedded memories in systems-on-chip environments. The fault models are being developed using multidimensional device modeling and simulation tools that provide dimensional control over individual process layers. These fault models are validated with physical experimentation. The on-chip test methods include combining the dynamic power supply current, iDDT, with traditional deterministic BIST to reduce defect escapes. High-speed iDDT testing circuits are being developed to catch frequency-dependent faults. This project is being developed in collaboration with Intel Corporation.
