The research funded by this CAREER grant is addressing three of the microprocessor design challenges posed by deep submicron technologies: slowing performance growth, decreasing reliability, and increasing power dissipation. This research is attacking these challenges by proposing new technology-sensitive designs across three design categories: individual microarchitectural cores, large on-chip memory systems, and chip multiprocessors.
The microarchitecture research is organized into two parts: a technology-based scalability analysis of current microarchitectures, to determine and quantify future microarchitectural bottlenecks, and an evaluation of the grid instruction processor--a new microarchitecture, containing two-dimensional arrays of functional units, which eliminates many of the microarchitecture bottlenecks that will arise from advancing technologies.
The research is also evaluating how multi-megabyte on-chip memory systems should be designed in future wire-dominated environments. Both the physical design (which will have sub-banks numbering in the thousands) and the logical organization (how to map data into caches with non-uniform, position-dependent latencies) are being explored.
Finally, the funded research is exploring ways of accelerating single-thread performance by adding new mechanisms to chips with multiple processor/memory tiles each. These mechanisms include fine-grained computation migration, dynamic thread parallelization, redundant computation, and working set size-based dynamic allocation and adjustment of on-chip memory.
