The objective of this NSF CAREER research is to develop process variation aware design methodologies for the synthesis of embedded systems in nanometer scale CMOS technology. Many embedded systems are heterogeneous multiprocessor system-on-chip (MPSoC) architectures. The reliance on deep sub-micron process technologies for the fabrication of embedded multiprocessor system-on-chips gives rise to concerns about process variations, which can cause significant performance variations for a design. Although designing for worst-case process margins is the traditional approach to deal with outliers, the degree of variability encountered in the new process technologies makes this option nonviable. The existing deterministic embedded system design methodologies may result in unexpected performance discrepancy or a pessimistic performance estimation, and may end up using excess resources to guarantee real-time constraints, due to overly conservative design approaches.
This research proposes a design paradigm shift from today's deterministic design to statistical or probabilistic design. Specifically, this proposal aims at: (1) developing hierarchical statistical analysis methodologies to facilitate embedded MPSoC synthesis; (2) developing process-variation-aware hardware synthesis techniques; (3) developing process variation aware software worst case execution time (WCET) analysis and optimization techniques for embedded applications; (4) developing process variation aware hardware/software co-synthesis techniques. The education part of this program includes: the enhancement of existing curriculum by integrating new course modules on process variations to complement and upgrade the core courses; the broad dissemination of the results via research publications, courses, seminars, tutorials, and workshops; and the development of software components that are disseminated to the research community and beyond.
Embedded computing systems are of great economic importance, used for applications such as consumer electronics appliances, automobile control, aircraft autopilot, and medical instrumentation. Compared to high-performance computing systems, embedded systems are usually more cost-sensitive and require shorter time-to-market, and many of them need to satisfy real-time constraints. ESL (Electronic System Level) design methodology is usually employed to design a heterogeneous system, which consists of embedded processors and application-specific integrated circuits (ASICs). Designers have resorted to technology scaling (i.e., using smaller transistors to build integrated circuits) to enhance performance. The reliance on deep sub-micron process technologies for their fabrication has brought the concerns of delay/power variations to the forefront. The manufacturing variations and circuit aging effects can cause significant performance and power variations for an identical hardware design over a lifetime of the embedded system products. The majority of the prior analysis and optimization techniques related to delay/power variations are at the lower level (device or logic gate level). It is important to raise the process variation awareness to a higher level, because the benefits from higher-level optimization often far exceed those obtained through lower-level optimization. Furthermore, higher-level statistical analysis enables early design decisions to take lower-level process variations into account, avoiding late surprise and possibly expensive design iterations. This CAREER project recognizes this need and proposes a holistic solution, which combines high-level synthesis, hardware/software co-synthesis, and software techniques, to design variation-aware embedded multiprocessor system-on-chip designs. The key outcome of this projects includes research products (including publications, software, and course development) with broader impacts in the following subjects: (1) We propose variation-aware analysis and synthesis algorithm for Embedded Multiprocessor System-on-Chip (MPSoC) architectures to mitigate the impact of delay/power variations. A new design metric, called performance yield, defined as the probability of the assigned schedule meeting the predefined performance constraints, is used to guide the task allocation and scheduling procedure. An efficient yield computation method for task scheduling complements and significantly improves the effectiveness of the proposed variation-aware synthesis algorithms. Research outcomes were published in top EDA (electronic design automation) conferences such as DAC, ICCAD, ASPDAC, DATE, and top IEEE/ACM journals such as TCAD/TVLSI, with best paper award from ASP-DAC 2008, ISLPED 2010, and multiple best paper nominations. (2) In addition to manufacturing variations, high operational on-chip temperature can also cause circuit aging effects (i.e., the performance degradation of an electronic system can happen over time due to the reliability mechanisms). We propose novel performance degradation models for digital circuits, taking into account of the temperature impacts. We also propose novel optimization techniques to mitigate the performance degradation. Our research outcomes received best paper award in ISVLSI 2012. (3) Emerging memory technologies (such as spintransfer torque RAM (STT-RAM), phase-change RAM (PCRAM), and resistive RAM (RRAM)) are being explored as potential alternatives to existing memories in future computing systems. Such emerging nonvolatile memory (NVM) technologies combine the speed of SRAM, the density of DRAM, and the nonvolatility of flash memory, and so become very attractive as alternatives for the future memory design in embedded systems. Such emerging memory technologies also have reliability issues such as process variations and wearout issues. In this project, we studied the impact of process variations' impact on the memristor-based RRAM. Based on our analysis, Monte-Carlo simulations are conducted to evaluate the device mismatch effects in the memristor-based memory. (4) Most of the research findings have been integrated into the graduate level courses and undergraduate courses. The PI was also invited to give talks in various companies/universities, and gave tutorials in many international conferences. The PI was also selected as ACM Distinguished Speaker and IEEE Computer Society Distinguished Visitor to disseminate the knowledge created in this project. (5) The project involved both graduate students and undergraduate students to conduct scientific research activities. Two students received Ph.D. degree due to their contributions in this project. Four undergrauate students were involved with the support of REU (Research Experience for Undergraduate) fundings from this project.
