As multi-core systems become the major computing platform, efficient cache management is even more crucial to system performance and power efficiency than before. An effective approach is to use software cache management (SCM) with hardware supports to manage shared last-level cache, because sophisticated SCM may adapt to the complex scenarios of cache usage on multi-core processors.

A critical and unsolved issue in SCM is the lack of rich and relevant information for software to reason about cache performance under different configurations. The project investigates the use of lightweight and Reconfigurable hardware Cache Emulators (RCEs) to extend the capability of SCM. With this new hardware support, sophisticated SCM algorithms that constantly monitor cache usage through RCEs are developed. Those SCM algorithms aim to improve cache power efficiency by turning off unused cache portion, optimize cache partitioning for multi-core processors, and improve software-controlled cache mapping to improve cache utilization.

The research will improve system performance, power efficiency, and performance predictability for laptop, desktop and server computers using multi-core processors of large shared caches. It may make an impact on industry processor design to include lightweight RCEs as well as enrich SCM algorithms. It will also introduce new educational materials for students to study multicore cache management through hand-on experiments.

Agency
National Science Foundation (NSF)
Institute
Division of Computer and Network Systems (CNS)
Type
Standard Grant (Standard)
Application #
1117604
Program Officer
M. Mimi McClure
Project Start
Project End
Budget Start
2011-08-01
Budget End
2014-07-31
Support Year
Fiscal Year
2011
Total Cost
$360,345
Indirect Cost
Name
Iowa State University
Department
Type
DUNS #
City
Ames
State
IA
Country
United States
Zip Code
50011