Project Proposed: This project from an EPSCoR state, aiming to develop a highly scalable and reconfigurable multi-board-based testbed which can emulate and validate future large-scale many-core and system-on-chip systems, enhances the future for design of multi-core systems. Specifically, this testbed efficiently and effectively emulates all the functionalities that are perceived at both the network-on-chip (NoC) and the full-system levels. The proposed work establishes a high performance, multi-core testbed in Nevada, enabling the following research projects in system-on-chip design: - Emulation of new computer architecture designs, - Design space exploration for NoC-based many-core designs, - Emulation of hybrid photonic-electronic NoC architectures, and - Traffic modeling and benchmark development. The work aims to develop a flexible testbed for NoC architectures seen to be key to the future of multiprocessor design. In recent years, computer architecture speed-ups have begun to rely exclusively on multi-core paradigms instead of faster cores. There is a general consensus that these many cores have to be linked together through a functionally correct, power-efficient, and reliable on-chip communication architecture, now widely known as network-on-chip. Testbeds of this type are critical to economic vitality in the computer industry. Broader Impacts: This instrumentation should provide a unique research facility for faculty and graduate students to conduct research on NoC architecture technology and education. The testbed will be made available to researchers around the country through a cyberinfrastructure remote access mechanism. The proposed testbed enhances Ph.D. production in an EPSCoR state and solidifies UNLV?s position in NoC architecture research.
