Future systems based on nanoscale transistors will offer significant boosts in information gathering and processing capabilities. However, the reliability and scalability challenges mandate a transformation in the system-level approaches. A number of fundamental assumptions will change with nanoscale transistors: the fabrication processes will be highly defective due to the random nature of nanoscale self-assembly; system reliability cannot be guaranteed in the field because nanoscale transistors are extremely susceptible to intermittent faults; system scalability demands the interconnection between components to be strictly localized.
This research aims at forming a new paradigm to construct reliable and scalable nanosystems, which will open up new application domains currently held back by the size and power limit. This research focuses on three life-span stages of future nanosystems: (1) defects discovered during manufacturing are treated through chip reconfiguration; (2) dynamic faults are treated in the field with built-in redundant elements under the strict constraint of local interconnections. The approaches and analysis for these two stages will provide guidance for the (3) system design stage.
This CAREER project includes a strong educational component for undergraduate students to participate in a number of competition projects to gain research experiences. These projects are also joined by graduate students to learn to convey research outcome to a general audience. Such an integrated research and educational effort aims at bridging the gaps between state-of-the-art research and the teaching of engineering approaches, many distinct knowledge bodies of EE, CE, and CS, and between systems research and device research in the academic community.
