The evolution of network routers and switches has been driven primarily by performance. Recently, thanks in part to the emergence of large datacenter networks, the need for better control over network operations, and the desire for new features, programmability of routers has become as important as performance. In response, researchers and practitioners have developed reconfigurable switching chips with a RISC-inspired pipeline architecture, which provide some programmability through hardware primitives that can be configured into a processing pipeline with software directives. Reconfigurable switches are gaining traction as they perform the same as fixed-function chipsets but with lower area overhead.
This project seeks to extend the state-of-the-art by developing higher-level programming abstractions and traffic management algorithms for reconfigurable switches. This project will investigate: 1) a C-like language and an abstract machine representing modern switches, 2) a compiler to convert the transactional specification to the pipelined abstract machine, and a 3) Push-In, First-Out (PIFO) primitive for programmable packet scheduling.
This project will make programming high-speed switches easier and more expressive, which will be useful in datacenters, enterprises, and service provider networks. Research findings will be incorporated into the undergraduate and graduate curricula, offering students an opportunity to implement network protocols in C, a familiar language, but run them at hardware speeds. The course material will be made widely available through MIT OpenCourseWare and on the MITx MOOC.
