This proposal was submitted in response to the solicitation "Nanoscale Science and Engineering" (NSF 00-119). We propose a joint Caltech/NASA-JPL/Agere Systems research program to develop new materials for Si nanocrystal nonvolatile memories and related nanoscale electronic devices. Under the program:
o New aerosol-based Si nanoparticle and nanowire engineering methods will be developed to enable formation nanoparticle and nanowire arrays with precise control of particle size, particle number and array structure. These methods 'will be compatible with Si ultralarge scale integrated (ULSI) circuit process technology. o Aerosol-synthesized and colloidally processed silicon nanoparticle and nanowire arrays with novel configurations will be integrated into Si-based metal-oxide-semiconductor (MOS) devices at state-of-the-art device dimensions yielding nanometer-scale memory devices. o A dielectric heterostructure layered tunnel barrier will be developed to achieve simultaneous ultrafast chargc injection and extremely long charge retention times, which are mutually exclusive for existing conventional dielectric tunnel baffler designs. o Nanocrystal charging via electrical injection and photoexcited carrier injection will be studied to assess layered tunnel barrier performance and to determine whether quantum size effects on the density of electronic states can be exploited for control of electronic charging energy.
The focal point of the work is a recently demonstrated high-performance aerosol silicon nanocrystal memory device, developed by the present nanoscale interdisciplinary research (NIRT) team under prior NSF support. Silicon nanoparticles comprise the floating gate that is the storage node of a nanocrystal nonvolatile memory. Aerosol synthesis allows control of Si nanocrystal size and shape that are difficult to achieve by other synthesis methods. Uniquely, our team has successfully integrated vapor-synthesized aerosol nanoparticles into a high-performance silicon-based electronic device, fabricated at 0.18 micron design rules on 200 mm substrates by ultraclean processing at state-of-the-au device dimensions. Extensive electrical characterization of transistor subthreshold and turn-on performance, retention time, program-erase cycling, gate and drain disturb characteristics indicated that these devices are high performance memory devices. The Caltech/JPL/Agere NIRT team is unusual in its combination of basic research on new electronic materials developed at Caltech followed by direct materials integration into a flexible, state-of-the-au silicon device process carried out at Caltech and Agere System's fabrication facilities.
