Intellectual merit: This project is awarded under the Nanoelectronics for 2020 and Beyond competition, with support by multiple Directorates and Divisions at the National Science Foundation as well as by the Nanoelectronics Research Initiative of the Semiconductor Research Corporation. Progress in transistor and integrated circuit (IC) scaling has slowed, in part because of physical limits of transistor operation at small dimensions, but primarily because power consumption and power density are becoming excessive as complexity and density are further increased. IC power density results from opposing constraints in transistor and circuit design; the electron thermal distribution sets a minimum transistor control voltage for low off-state dissipation, while the dissipated energy on interconnects increases as the square of voltage. Addressing these limitations, radical changes in transistor design are proposed. To increase the on-current, designs are proposed that will overcome the so-called density of states (DOS) bottleneck in III-V semiconductors, adding additional valleys to those used in transport, therefore increasing the amount of charge that can be transported through the device at a high velocity. To increase drive current in N-channel field effect transistors (FETs) and the IC speed at reduced voltages III-V transistors will be develop using for the first time transport in the L (satellite) valleys, i.e. L-valley electronics. These will use the light electron part of their dispersion in the transport direction for fast carriers and will use the heavy electron characteristics to pack multiple bands into the ?same? energy space. Similar density of states engineering will be applied to P-channel FETs, achieved using light- and heavy-hole states mixed by strain and quantum confinement. To reduce supply voltages, steep transistors will be developed, having I-V characteristics varying much more rapidly than a thermal distribution. In addition to established tunnel injection devices having only moderate on-current, high-current steep-FETs will be developed. These use transport in energy bands of tightly constrained energy range, produced using 1-D semiconductor superlattices. Combining these two classes transisto rs, state-density-engineered transistors designed for high drive currents at low voltage, and steep transistors designed for very low off-state leakage, the program will explore new logic gate designs providing low power and high speed.

Broader Impacts: The proposed work seeks to increase the speed and complexity, and reduce the power consumption of ICs. The industry is of enormous worldwide value. The participants interact regularly with the VLSI industry, communicating ongoing work and seeking guidance, and will continue with this model in the NSF program. Development of high-speed yet low-power logic devices will circumvent present power-consumption limits now constraining VLSI speed and complexity. This program will enable further large increases in the speed and power-limited computational performance of ICs, benefiting applications in industry, commerce, and personal use. Ph.D. students will be trained in semiconductor materials, device physics, and IC design. Their training will emphasize the interaction of system and circuit design with device design. Simulation tools will be developed and distributed by nanoHub to a worldwide user community. The program will operate a summer internship program, affiliated with that of the NNIN, providing laboratory experience exposure to a research environment for 8 undergraduate students.

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University of California Santa Barbara
Santa Barbara
United States
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