Intellectual Merit: On-chip radio-frequency (RF) wireless communication will be investigated to propose a unified design framework for its applicability on contemporary Multi-Processor System-On-Chips (MPSoCs) in 2D and 3D semiconductor technologies. RF wireless communication will be established with multiple antennas on the same die for a 2D integrated circuit (IC), or multiple antennas and/or couplers on the same 3D IC package. In order to enhance these on-chip wireless communication channels, novel approaches in reconfigurability of wireless interconnects will be utilized, as well as exploring the applicability of various wireless communication schemes of the proposed research is in leveraging the diverse knowledge in wireless communications to improve the MPSoC performance in computing and power efficiency. Performance profiling of proposed communication circuits and channel quality will be examined on a network-on-chip system to observe the direct impact of proposed novelties in MPSoC efficiency, highlighting trade-offs in physical, wireless, channel and communication quality and the MPSoC computing efficiency.

Broader Impact: Proposed research will enable the next generation of low-power, increased functionality ICs, as well as providing a high performance interconnect for current and future (i.e. 3D IC, MPSoC) microelectronic devices. Wireless interconnects are a vehicle to alleviate the power wall and communication challenge in contemporary MPSoCs and enabling the further scaling of complementary-metal-oxide-semiconductor technology by replacing the power-hungry wire-based interconnects. Impacts on education include those generated by new course modules developed to integrate in undergraduate-level wireless communications and very large scale integration (VLSI) design courses, a new graduate course, student projects (independent and research experience for undergraduates projects) and outreach to high-school students to promote science, technology, engineering and mathematics disciplines. Investigators are proactively participating in outreach activities to create synergy in VLSI and wireless communities, including a recent newsletter article on wireless interconnects to 3000+ recipients in the VLSI community.

Project Start
Project End
Budget Start
2012-09-01
Budget End
2016-08-31
Support Year
Fiscal Year
2012
Total Cost
$432,000
Indirect Cost
Name
Drexel University
Department
Type
DUNS #
City
Philadelphia
State
PA
Country
United States
Zip Code
19102