The Main Amplifier The main amplifier has been completely redesigned, it now accommodates two headstages of either Seris or Serp designs. Both may be used at the same time. This amplifier connects directly to the data acquisition system in the computer being powered by a 5 volt supply from the computer through a DC to DC voltage converter located on the amplifiers main board. This allows the electronics to be powered without the introduction of main power to the analog electronics, or its enclosure. For each head stage channel the signal is first passively filtered and then amplified by 10x - this gain being jumper selectable - and fed to one of the 8 channels of the data acquisition system (DAQ) and to the front panel of the amplifier. This signal is also sent to another amplification stage with a gain of 100x (also jumper selectable). In order to resolve the submicrovolt signals generated by the Seris and Serp systems operating in a small gradient, without exceeding the dynamic range of the DAQ system, this final amplification stage subtracts out a voltage determined by one of three methods. In Mode 1 the signal from the first stage is fed into a integrator and the integrated signal is subtracted at the input of the next stage. This allows amplification of signals at frequencies faster then the integration time (dt). This is the mode we are currently using. In Mode 2 the signal from the first amplifier gates to a sample-and-hold amplifier. The value stored in the sample-and-hold amplifier is subtracted from the final amplification stage. At periodic intervals the computer puts the sample-and-hold amplifier in sample mode, thus zeroing the output. This is usually done at the probes negative position (away from the cell). This mode is in the experimental stage. Mode 3 uses a combination of Mode 1 and 2. In all cases the output of the final stage is then sent to the DAQ system and the front panel.
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