This research proposes a preliminary evaluation of enabling technologies for 100 TeraFLOP class computers. The research is broadly classified into the following parts: architectures (single node architecture, parallel architecture), system software (languages, compilers, programming tools and environments), algorithms (design models, performance and scalability) , and applications (scaling and realizable performance). Single node architectures for future generation computers will exploit considerable implicit parallelism. Candidate technologies for single node architectures include super-scalar execution, very long instruction words, simultaneous hardware multithreading, and processors-in-memory. The PIs propose a processor architecture based on the VLIW with possible implementations using PIMs. Parallel architectures are based on clusters of these nodes in a hierarchical network. Due to the large number of computational units, algorithm design and scalability issues become critical. Hierarchical decomposition of problems with an emphasis on proper mapping to the underlying architecture is necessary. Whereas problems at higher levels must be loosely coupled, they can be very tightly coupled at lower levels. Alternate algorithm design methodologies and abstract machine models must be constructed. Finally, the scope of applications that can effectively use these architectures needs to be identified. This research will perform a study of each of these aspects of future generation computers. The PIs expect to draw heavily from their experience in the design of scalable parallel algorithms and architectures and from the CEDAR project.
