This research is on algorithms for synthesis and layout of VLSI designs. Algorithms for complex, large industrial type design problems are being developed. Topics include: (1) high level synthesis with testability as a goodness measure, (2) timing driven placement for FPGAs, (3) channel and switchbox routing in which cross talk considered, and (4) application of optimization techniques to enhancing the effectiveness of the fabrication process. Approaches include: assessing the effects of register allocation and binding on testability; use of neighborhood graphs to guide iterative design; and integer programming to solve routing problems. Software incorporating the algorithms as design tools is also being developed.
