High speed, high volume cryptographic systems will form the basis for the security of video, wireless, and computer communications of the next decade. This research involves the design and development of such systems, especially that of hardware-based stream ciphers. High speed hardware-based stream ciphers can be easily manufactured, programmed, and implemented. They can be used to encrypt data (such as voice or video) in real time and are used as embedded components in cellular telephones, GPS satellites, radar, and radio systems. Most stream ciphers, however, have been found to be vulnerable to various cryptoanalytic attacks. This research involves the development and analysis of new architectures for stream cipher generators which have all the above advantages but which are much more secure than traditional architectures.
Linear feedback shift registers have proven especially useful for the generation of pseudorandom sequences for high speed communications. They have been intensively studied for over forty years and their usefulness does not appear to have any end in sight. Recently a fundamentally new architecture for feedback shift registers was discovered, the so-called feedback-with-carry shift register or FCSR. This architecture shares all the advantages of the linear feedback architecture such as high speed and ease of implementation, but the resulting pseudorandom sequences are also more secure. This research involves a number of implementation issues for the new architecture including (1) the development of parallel circuitry for high speed generation of pseudorandom sequences, (2) the design of combiners and feedforward functions to further increase the security of FCSR sequences, (3) the design of clock-controlled FCSR circuits, and (4) the analysis of the cryptographic security of the FCSR sequences which are generated in this way.
