Our research goal is to improve quality level of CMOS ICs without performing the high-cost burn-in process. High-voltage screening schemes have been successfully developed and implemented to eliminate early-life failures due to oxide defects in digital CMOS circuits. However, the success is not extended to its analog counterparts due to their working conditions and circuit topological structures. This project proposes to develop efficient yet effective high-voltage stress test process for analog circuits. The research objective is to develop the framework of an automatic stress test system for analog/mixed-signal circuits, where the system integrate three major components: stressability analysis, stressability design methodologies, and stress test process. The component of stressability design methodologies include a stress vector generation process and a stressability enhancement process. The stress test process generates the test programs with the defined stress conditions for the circuits under test.
The success of this development will enable the analog circuit to be stressed properly using high-voltage screening to eliminate early-life failures due to oxide defects and to enhance reliability and quality of CMOS ICs without performing high-cost burn-in screening.
