This research focuses on devising novel techniques based on data-flow analysis in the memory management of real-time multidimensional signal processing. Data-flow analysis is the steering exploration mechanism along this project, allowing more exploration freedom than the traditional scheduling -based investigation, since the memory management tasks usually need only relative (rather than exact) lifetime information. Moreover, data-flow analysis enables the study of memory management tasks at the desired level of granularity -- between whole array and the scalar level -- trading-off computational effort and solution optimality.
Part of this project investigates non-scalar methods for computing the memory size in real-time multimedia algorithms. This research addresses novel memory computation topics: dealing with a large class of parametric specifications, and dealing with parallelism in high-throughput applications. This project addresses also the problem of deriving a multilevel memory architecture optimized for area and/or power, subject to performance constraints. Another research direction is the optimized mapping of data from an embedded application code into the on-chip SRAM or the off-chip DRAM for maximizing the overall memory access performance of the application.
The educational component of this research includes (1) the development of a graduate course covering algorithmic aspects of high-level synthesis and system design methodologies; (2) the development of a web tool for memory size computation.
