This project investigates new architectures for domains such as cryptography, signal processing, and error correction, where the applications are highly parallel. Traditional microprocessor architectures will not efficiently scale to exploit the parallelism present in these applications. Hardware design for these applications is too expensive, risky, and inflexible. Reconfigurable computing, which attempts to combine programmability with hardware performance, has logistical problems that will prevent its widespread adoption. This project will develop and evaluate architectures that combine the portability and abstraction of software development with the performance of reconfigurable hardware. This will be done by converting a serial representation of an application into a spatial representation, and executing the spatial representation on a fabric of locally interconnected processing elements. The conversion from serial to spatial representation will be performed at run time, concurrently with execution.
The first phase of this project will involve the definition and prototyping of a first generation of this architecture. The second phase of the project will refine the code generation techniques for the architecture. The third phase of the project will investigate the incorporation of various control-flow operations in the architecture.
