This project will pave the technological pathway for scaling silicon transistors down to atomic dimensions (~1 nm minimum feature size). A promising new transistor structure (the back-gated thin-film MESFET) will be developed, one that is more scalable and much simpler to manufacture than the conventional MOSFET structure employed in integrated-circuit (IC) devices today. The MESFET will provide for tremendous gains in functional density, not only by transistor scaling but also by three-dimensional integration (stacking multiple layers of transistors in an IC) for maximum circuit layout efficiency and system performance. This work will enable improvements in performance and cost to continue for at least 20 more years, supporting the growth of the semiconductor industry over this time period. It will also serve to bridge the technological gap between CMOS devices (scaling limit ~10 nm) and molecular/nanotube devices (~1 nm minimum dimensions), while easing the manufacturing challenges of nanometer-scale fabrication. Given the key role of information technology and emerging role of nanotechnology in modern society, this project will have very broad impact. Graduate and undergraduate students will directly benefit from it via hands-on research and course lectures, and new knowledge will be disseminated widely via presentations at international workshops and conferences, as well as in archival journals.
