In the not too distant future, semiconductor designs are expected to integrate billions of transistors on a single chip and will operate at frequencies in excess of 10GHz. This dramatic progress will introduce unforeseen challenges and will require dramatic changes of the tools and methods used to design highperformance processors. With high operating frequencies, accurate performance verification of the design will be come paramount. At the same time, noise in the design will rise to dramatic new levels due to the coupling between closely spaced devices on the same die. High noise levels will impact the performance by slowing down the critical delay paths in a circuit and will therefore threaten the achievable operating frequencies. We therefore propose new methods for the analysis of processor performance in the presence of high-noise levels. Furthermore, we intend to develop new methods for performance optimization in noise dominated circuit environments for future high-performance processor and systems-on-chip designs.
