As the amount of test data required to test new generations of complex system-on-chip (SOC) designs continues to grow rapidly, conventional external testing approaches where all test data is stored on the tester and transferred to/from the chip is becoming increasingly difficult. Testers have limited speed, memory, and I/O channels. The limited test data bandwidth between the tester and the chip is becoming a major bottleneck that is projected to become much worse. This project involves developing hybrid schemes that combine external testing and self-testing approaches in novel ways to ease the burden on the external tester. Such techniques can provide the best of both worlds. The overhead and fault coverage limitations of self-test approaches can be overcome by intelligently making use of deterministic data from the tester to guide the self-test hardware, while the test data bandwidth and storage requirements for the external tester can be reduced by orders of magnitude. Some of the questions to be answered in this research include:
1. What are the most efficient ways to use deterministic data from the tester to guide test pattern generation hardware on the chip. 2. How to minimize the hardware under a constraint on test data bandwidth from the tester. 3. For a system-on-chip (SOC) with multiple cores, what is the best way to configure the hybrid test hardware for each core. 4. How can deterministic data from the tester be used to reduce power dissipation during self-test. 5. How can delay fault coverage be improved with a hybrid scheme.
