The notion of prototyping is pervasive in engineering design; one investigates the viability of a new idea by constructing a single implementation, a prototype. Whether the problem is designing an integrated circuit transceiver, a micromachining-based thumbnail-sized chemical agent detector, or an aircraft, the cost and time required to construct prototypes is high enough to discourage comprehensive design exploration. It is possible to dramatically reduce the need for physical prototypes by substituting computer models, a process referred to as computational prototyping. The promise of using computational prototyping is that the ease of testing alternative designs will allow designers to examine more radical, and possibility much more efficient, design alternatives. The challenge of computational prototyping is in developing accurate modeling algorithms and techniques which are both flexible and fast enough to allow designers to examine a wide range of design alternatives.
For complicated systems, which may have millions of interacting components, computational prototyping using direct numerical simulation is too slow for designers to use in design exploration. Instead, it is necessary to exploit hierarchy in the computational prototype, and most hierarchical computer verification and optimization tools rely on manually generated high-level models for function blocks in the design. This ``by-hand'' process is time-consuming and error-prone, and interferes with rapid deployment of new technology. For this reason, there is strong interest in developing techniques which automatically generate accurate high-level models from more detailed numerical simulation.
Over the past decade, substantial effort has been devoted to finding automatic strategies for extracting high-level models from linear interconnect and packaging. This effort was successful in a very practical sense, commercial computer-aided companies now provide users with a wide range of very sophisticated techniques for extracting high-level models of interconnect. Chip designers are no longer required to be signal integrity experts. In addition, the research also substantially deepened the understanding of the general problem of model reduction. And it is from this only recently achieved vantage point that we now think we can start to tackle the next two problems: generating {it parameterized} reduced-order models for use in hierarchical optimization, and automatically reducing the nonlinear systems associated with micromachined devices or analog subsystems. We originally proposed to investigate both the problems of nonlinear model reduction and parameterized model reduction. With the reduced budget, we will investigate only the nonlinear model reduction problem, to automatically generate low-order models of micromachined devices and analog subsystems. We will be examining strategies involving nonlinear generalizations of balanced realizations, and combining such strategies with trajectory piecewise linearizations to generate accurate subsystem models.
