Rapid increase of manufacturing costs of the integrated circuit (IC) and the widening gap between the design productivity and manufacturing capacity may prevent the IC technology from continuing to advance according to the Moore's Law. Programmable devices offer an attractive solution for significantly lowering the amortized manufacturing cost per unit and dramatically improving the design productivity through re-use of the same silicon implementation for a wide range of applications. However, existing programmable circuits and architectures are not power efficient. In some cases, they may consume 100x higher power compared to customized IC designs. This project focuses on research and development of power-efficient programmable circuit fabrics and architectures and associated synthesis tools, and is aimed to reduce the power dissipation by over 10x. Our research will be guided by two key principles: (i) the use of a highly quantitative approach to circuit and architecture design and optimization; (ii) the integration of different levels of optimization techniques, from circuit-level to fabric-level and system-level, and finally synthesis tools, for developing novel programmable devices with the highest power efficiency. Outcome of this research includes: (1) A flexible power evaluation framework to enable accurate quantitative evaluation of programmable logic devices; (2) Novel circuits and fabrics to reduce leakage and dynamic power in programmable devices; (3) Novel implementation of clock gating and power gating for dynamic power management; and (4) effective and efficient algorithms and tools to support the aforementioned circuit-level, fabric-level, and system-level optimization techniques.

Broader impacts of this project include (1) Timely dissemination of research results and technology transfer to enable new applications of programmable devices that can significantly benefit the overall information technology (IT) industry; (2) Involvement of graduate and possibly undergraduate students in the proposed research and include the latest research methodologies/results into teaching, which will help to train future researchers and engineers for further advancement of the information technology.

Agency
National Science Foundation (NSF)
Institute
Division of Computer and Communication Foundations (CCF)
Application #
0306682
Program Officer
Sankar Basu
Project Start
Project End
Budget Start
2003-07-15
Budget End
2009-06-30
Support Year
Fiscal Year
2003
Total Cost
$306,000
Indirect Cost
Name
University of California Los Angeles
Department
Type
DUNS #
City
Los Angeles
State
CA
Country
United States
Zip Code
90095