Collaborative Research: Application Specific Architecture Customization and Co-Exploration
The embedded market demands processors that can achieve high levels of performance in the smallest possible area, while simultaneously minimizing power and energy dissipation. Customized processors offer a way of meeting these demands through targeted architectures specifically constructed to meet the performance, area, and power demands of a given application.
Our approach is different from the traditional ASICs design, since our focus is to bring the customization up to a higher level where we generate programmable reconfigurable processors that allow both the algorithm and architecture to be co-configured (configured together). Architecture customization is not able to realize significant gains until both the algorithms, data structures, ISA and certain architecture components can all be configured. This grant focuses on co-exploring the algorithm and architecture design space for speech, cryptographic and network processors to discover common customizable components. The goal is to identify customizable components from these application domains, so that they can be incorporated into an overall infrastructure for co-exploration.
To broader impact, this proposal will provide infrastructure to aid in the automated co-exploration of architectures and algorithms for industry and academic researchers. We will make this infrastructure available to aid researchers in exploring these and other application areas.
