Slipstream execution mode for multiprocessors involves running redundant copies of a parallel task on each processor in a dual-core chip multiprocessor (CMP). One copy of the task is shortened by removing synchronization events and stores to shared memory. This speeds up the execution of the other task through prefetching and other coherence optimizations enabled by a future view of shared memory references.
The first objective of this project is to implement slipstream execution mode on actual CMP-based hardware. Given a multiprocessor built from dual-core CMP's, each with shared L2 cache, slipstream mode can be implemented with no changes to hardware. This implementation will validate the utility and scalability of sliptream-mode prefetching on full-sized applications. The second objective is to automate and optimize the mechanism for local synchronization between the redundant tasks, known as A-R synchronization. The choice of mode, ranging from tightly coupled to loosely coupled, can significantly affect the performance of an application. The project will develop run-time and compile-time mechanisms to select the best A-R synchronization mode for an application or region of execution.
Slipstream execution mode is a new alternative for shared-memory parallel computation. As more systems are built from CMPs and multithreaded processors, it is imperative that we investigate efficient ways to exploit parallelism at all levels. Slipstream mode offers a performance boost for applications that cannot otherwise take advantage of additional thread-level parallelism. This work will impact important scientific applications, such as quantum mechanics and computational biology that use shared-memory multiprocessing to address large-scale problems.
