Co-Designed Virtual Machines use a combination of concurrently designed hardware and software to implement a conventional instruction set architecture (ISA). An implementation-specific instruction set is directly supported by hardware, and a co-designed dynamic binary translation system completes the processor implementation by translating binaries of conventional ISAs. Translated implementation-specific binary code is cached in a concealed region of memory and executed directly by the processor core. The obstacles to using this approach involve potentially detrimental overheads -- at startup, during steady state, and in required memory resources. The proposed research will tackle each of these overhead problem areas by 1) providing micro architecture support to improve translation times by an order of magnitude, 2) adding features to eliminate steady state overheads of executing cached translated code, and 3) using memory compression to reduce the fraction of physical memory that must be dedicated to holding translated code.
The co-designed virtual machine paradigm will greatly simplify the hardware design process and enable performance improvements by providing a better match between computer hardware and software. A simpler design process will lead to reduced design times, lower engineering costs, and hardware innovations coming to market sooner. Performance improvements will be accompanied by better energy efficiency because some hardware-intensive tasks are shifted to less- Frequently used software tasks.
