This project will investigate novel ways of optimizing value communication in microprocessors. The objective is to improve upon current value communication mechanisms that are typically agnostic of the communication requirements of the values being communicated. The researchers propose to develop and investigate novel value communication mechanisms that are optimized for the communication behavior of specific values, with the aim of greatly increasing processor performance.
The research will consider register and memory values in microprocessors. There will be two main themes in the research. The first theme will be to develop predictive techniques to learn about the communication requirements of values. The second theme will be to develop techniques that use knowledge of a value's communication requirements to optimize its communication. Specific schemes that will be investigated include optimizations to the register file, bypass network, dynamic scheduling window, load-store queue, and the cache hierarchy.
The research methodology will make extensive use of simulations using cycle-level simulators. The investigators will use a wide variety of benchmark programs including standard benchmark suites as well as other programs, including commercial workloads, written in a number of different programming languages.
