In the recent past, there has been a tremendous surge in the wired communications/wireless/high-speed IC manufacturing sector. While the design community has pushed the design envelope far into the future, the test barriers have not kept pace with the test requirements of high speed, integrated wireless and wired communications designs. Every IC that is manufactured, needs to be tested against its design specifications before shipment to the customer. As the speeds of these ICs increase, so do the requirements of the testers needed to test these ICs in manufacturing production. High-speed testers above 2 GHz are prohibitively expensive. Consequently, for speeds beyond a few GHz (2 - 25 GHz), built-in test (BIT) of high-speed/RF systems is a very attractive solution. Built-in test involves incorporation of test circuitry in the IC itself to facilitate the manufacturing test process. In this way, many of the test functions are performed "on-chip," alleviating the need for a high-speed (expensive) external tester. Since test cost is projected to escalate to about 40% of the total manufacturing cost of complex communications ICs in the near future, the use of built-in test is expected to significantly impact the cost of the manufactured ICs themselves and the ability of companies to compete in the marketplace. The core concept behind the proposed built-in test methodology is easy to follow. Instead of directly measuring the high-speed test specifications of the IC-under-test, a new paradigm for BIT of high-speed/RF circuits using alternate tests is proposed. Alternate tests are compact tests that are much more simpler to run than the original specification tests but contain as much information (or more) about the performance of the circuit-under-test as the original tests themselves. Furthermore, it is possible to design these tests so that pass-fail decisions can be made, based on analysis of analog signals using analog circuitry. In this way, two problems are solved: (a) that of being able to measure complex high-speed test specifications using simple on-chip test resources and a low-cost external tester, and (b) that of being able to analyze very high-speed signals (> 2 Ghz) without the need to digitize them (such digitizers are not available or are very expensive at these frequencies). The proposed work is interdisciplinary and will involve the use of concepts from computer algorithms, analog/RF circuit design, mathematics and statistics and fundamental electrical engineering and device physics.

National Science Foundation (NSF)
Division of Computer and Communication Foundations (CCF)
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Sankar Basu
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University of Florida
United States
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