The scaling of CMOS technologies is showing worrisome trends in terms of noise immunity, power consumption, reliability issues, and performance bottle necks. Major challenges are facing VLSI technologies in trying to maintain the current exponential growth in speed and density of devices. These physical challenges are resulting into an exponentially growing effort to maintain Moore's law. Hence, completely different alternative ways may be soon required to keep the hundreds of billions of dollars VLSI industry alive. Since their introduction, carbon nanotubes have been envisioned as the next leap in electronic circuits due to many attractive features such as their ability to act as both transistors and interconnect as well as photo devices. This multifunctional behavior is very desirable in building a single monolithic technology based only on carbon nanotubes that can perform every function available with silicon and GaAs technologies. Also, the speed and power consumption of these devices are expected to be immensely superior to CMOS technologies. In addition, there may be noise and coupling advantages when using metallic carbon nanotubes as interconnect relative to the typical metals used presently.
The proposed research will focus on the design, simulation, and testing of SWNT circuits and interconnects as well as extracting circuit and system level characteristics. The specific topics that the PIs and their groups plan to conduct under this project are: Accurate models and simulations of simple SWNT circuits using different logic styles. Comparison of different logic styles used for SWNTs and consequently a possible outcome of the best suitable style for SWNT circuits. Establishment of testing and fabrication techniques that are cost-effective, simple, and replicable. Modeling of metallic SWNT interconnects. Modeling of SWNT-metal based hybrid interconnects.
