The nanoarray, a crossbar consisting of two orthogonal sets of parallel nanowires, is a promising technology for the realization of memories and logic circuits at the nanotechnology level. Many design and manufacturing challenges need to be addressed before the feasibility of nanoarrays can be determined. In this project we will investigate and analyze new and existing nanowire types, create and analyze models for self-assembly of crossbars, explore large-scale nanoelectronics-based architectures for efficient memories and programmable logic arrays, model and develop techniques to handle defects and faults, and examine performance limitations associated with nanotechnologies. Project results will be broadly disseminated.
Advances in chip density reflected in Moore's law are becoming increasingly expensive to achieve. Early indications are that nanotechnology may provide an attractive alternative to lithography, the current method of chip assembly. It has the potential to increase logic density and memory storage capacity well beyond the levels achievable with lithography at a reasonable price. The nanoarray, a crossbar consisting of two overlapping orthogonal sets of parallel nanowires, is a promising technology whose new design and manufacturing challenges will be tackled by our team, consisting a chemist, an electrical engineer and an analytical computer scientist.
