Quantum-dot cellular automata (QCA) is a revolutionary computing paradigm well suited to nano-electronic implementation and scaling to molecular dimensions. In QCA, binary information is encoded in the position of single electrons among a group of dots forming a cell. In QCA, electrons switch between quantum dots within a cell, but no current flows between cells. This leads to extremely low power dissipation and avoids the problem of heat generation that ultimately limits the integration density of transistor circuits. QCA has moved beyond the realm of theory and experimental work-basic QCA devices and logic elements have all been constructed in metal. Our goal is then to develop the first physical design automation toolset that will help to generate computationally interesting, yet implementable circuits in QCA, and significantly expand QCA's existing systems-level infrastructure. We leverage our ties to physical scientists who are working to build real QCA devices. Based upon this interaction, a set of near-term buildability constraints has evolved: essentially a list of logical constructs that are viewed as implementable by physical scientists in the nearer-term. Until recently, most of the design optimizations have been done by hand. Then these initial attempts to automate the process of removing a single, undesirable, and unimplementable feature from a design were quite successful.
We now intend to use CAD, especially physical layout automation, to address all undesirable features of design that could hinder movement toward a buildability point in QCA. The net result should be an expanded subset of computationally interesting tasks that can be accomplished within the constraints of a given buildability point. CAD will also be used to project what is possible as the state-of-the-art in physical science expands. Our QCA placement, the first step in QCA physical design automation, is divided into zone partitioning, zone placement, and cell placement steps. The purpose of zone partitioning is to initially partition a given circuit such that a single clock potential modulates the inter-dot barriers of all QCA cells within each zone. The zone placement step takes as input a set of zones; each zone will have been assigned a clocking label that will ensure QCA signals arrive at the proper place at the proper time. The output of zone placement is the best possible layout for arranging the zones on a two dimensional chip area. Finally, cell placement will visit each zone and determine ideal locations for individual QCA logic gates.
