Design of scalable, high performance, area and energy efficient network-on-chip (NoC) architectures has emerged as a critical issue for orchestrating the system-on-chip (SoC) design paradigm. However, unlike the traditional multiprocessor interconnects, design of NoC architectures poses a whole set of new challenges in terms of on-chip area budget, energy efficiency, and reliability. The motivation of this research is to explore the NoC design space considering four closely intertwined issues. These are area constraint design and analysis of NoC architectures, developing detailed energy models for on-chip interconnects, designing suitable fault-tolerant techniques and reliability models, and developing a comprehensive testbed for conducting performance, energy and reliability tradeoffs in designing NoCs.
Since on-chip interconnects are predicted to be the performance bottlenecks for SoC architectures, the success of this research is likely to have a significant impact on the design of future SoCs, which are increasingly used in a wide range of applications. The simulation/analytic tools and techniques developed in this research will be used for training undergraduate and graduate students. The tools will be available through our Web site for use by other researchers, and we envision direct transfer of our ideas to industry.
