Consumer electronics and high-end computing applications of the future demand improved performance, better energy-efficiency and lower cost. A number of design styles have emerged to meet related tradeoffs, including such recent advances as structured ASICs. However, a fundamental change is upon us with the impending slow-down of Moore's law in 10-15 years-the size and performance of individual transistors are not going to improve as fast as today, and competitive semiconductor products will have to use spatial resources on a chip more efficiently. Such improvements will require synergies between computer and electrical engineering, as well as large-scale mathematical and combinatorial optimization. The challenges to interconnect scaling that arise in semiconductor technology nodes below 180nm give us a glimpse of problems to come. First, interconnect delays do not improve as fast as gate delays. Therefore, in chips that started shipping two years ago, critical interconnect delay exceeds gate delay. Moreover, today interconnects occupy a much larger volume on a chip than gates, and therefore gates must be spaced further apart to facilitate routing. By mitigating capacitance between adjacent wires, "unused space" improves power dissipation and signal delay, while decreasing signal noise. These global effects have not been expected in the late 1990s and devalue, to a large extent, the ongoing miniaturization of CMOS transistors. In technology nodes below 65nm, wires become so slow relative to gates that they must be heavily buffered during layout, making buffers most heavily used gates. In other words, most of the gate-area is used for communication rather than for computation. Since buffer locations and densities are not known in advance, additional unused space must be left throughout the chip, and interconnect becomes even longer.
The scaling effects outlined above already require a rethinking of methodologies for designing circuits and systems. Logic circuits must be synthesized so as to minimize communication and interconnect rather than gate area. At the system level, global communication and global wires must be minimized. Latency can be hidden by deep pipelining, non-traditional signaling strategies and such fundamental new concepts as networks on a chip. An additional thrust of this proposal is to carry over spatial planning to much earlier stages of chip and system design than is common today. The project will develop new software tools for optimizing shapes and relative locations of large modules, and inter-module communication at the system level. Spatial planning additionally requires attention to large fixed-shape modules, e.g., embedded memories and design Intellectual Property, that are difficult to pack and may require alignment. The more futuristic part of the research will consider spatial planning and physical optimization in the context of carbon-based nano-devices, quantum dots and quantum circuits. These technologies employ radically different types of interconnect and imply different design constraints and optimization.
