Future advances in high-performance, consumer, and embedded computing will be limited by power and thermal issues. As we seek to develop novel computing devices for these domains, it is critical to understand the power requirements at the earliest stages of the design and development process. This project will develop an accurate and flexible modeling infrastructure that can be used to quantify power, performance, and design complexity and will utilize this infrastructure to explore future power-aware computing design decisions.
This project seeks to develop novel technical solutions to architectural power and cycle-time modeling and to the problem of quantifying design complexity. The proposed models combine the flexibility advantages of analytical models with the superior accuracy that fully-empirical models provide. In this methodology, detailed empirical characterization of active power, leakage power, and delay is performed on building blocks and analytical models are then developed to chain them appropriately to model microarchitectural structures. These models will be applied to study architectural design tradeoffs between power, performance, and design complexity. In particular, this project seeks to understand the relative power-performance efficiency and design complexity of embedded and high-performance architectures and methods for extracting parallelism at the instruction and thread-level.
