NSF Proposal#: 0448534 Dr. Xiang-Dong (Sheldon Tan) Tan
University of California at Riverside
This research seeks to develop an integrated research and education program on behavioral modeling, simulation, and optimization techniques to address and overcome the mixed-signal (MS) system-on-a-chip (SoC) design challenges and enable a leap to a new generation of mixed-signal VLSI systems. The focus is to develop efficient techniques for modeling, simulation and optimization of MS SoCs designs, which consist of both analog and digital blocks and operates in mixed frequency ranges (base-band frequency or radio frequency (RF)). The project specifically targets at (a) development of efficient parametric behavioral modeling and hierarchical piecewise linear (PWL) nonlinear modeling techniques based on a graph-based approach for linear and nonlinear analog circuits; (b) investigation of efficient algorithms for optimizing analog circuits and on-chip power-delivery systems for MS-SoC circuits based on modeling techniques. The new modeling techniques will explore a determinant-design diagram (DDD) based symbolic analysis method to construct behavioral models that consider device parameter ranges and design variations to cope with increasing manufacture uncertainty. For modeling nonlinear analog circuits, DDD-based hierarchical piece wise linear (PWL) modeling techniques will be investigated, which promises high fidelity behavioral modeling of very large nonlinear circuits at various abstract levels. As more physical effects become prominent, design practice, especially for the analog circuits, has become an optimization-like process because performance, reliability and manufacturability specifications have to be satisfied or optimized simultaneously. Such optimization-like design paradigms require new different design strategies and methodologies from that of digital circuits and will be explored in this research. The education component of the program consists of development of new curriculum in behavioral modeling, simulation and optimization of MS SoCs, and exploration of innovative learning approaches via web-enabled instructional tools and project-oriented learning for the education of future engineers with the knowledge of behavioral modeling, design and verification for mixed-signal SoCs. Engineers very versed in MS VLSI design and MS CAD development will be trained under this research project.
", CCF-0448534. PI: Sheldon X.-D. Tan This CAREER program seeks to develop an integrated research and education program on behavioral modeling, simulation, and optimization techniques to address and overcome the mixed-signal (MS) system on- a-chip (SoC) design challenges and enable a leap to a new generation of mixed-signal VLSI systems. The project has the following outcomes: First, we developed a number of new techniques to perform compact modeling and reduction of linear networks for both digital and analog/RF circuits. We proposed a new hierarchical project-based model order reduction technique for scalable reduction, a new terminal reduction algorithm and a novel terminal-merging technique to deal with networks with large number of terminals. We also develop the first second-order passive truncated balanced realization reduction technique (TBR) for TBR-based reduction of networks with inductive elements. We also proposed the first decentralized model order reduction technique to mitigate the difficulty of reducing circuits with large number of terminals. We also proposed a new wideband adaptive reduction technique to perform error-controlled reduction for highly accurate modeling and reduction of interconnect circuits for the first time and implemented the algorithm into our UiMOR reduction tool. Second, we developed a number of advanced symbolic analysis techniques for analog modeling. The new algorithms consist of the hierarchical symbolic analysis to deal with large analog circuits and wideband s-domain realizable reduction techniques and a new Boolean algebra based graph-based symbolic analysis technique, which further improves the capability of symbolic analysis technique. The graph-based symbolic analysis developed by PI remains the state of the art of symbolic technique and was highly cited with many follow-up research works. Third, we proposed a set of algorithms to analyze and optimize the on-chip power grid networks. The algorithms include the extended truncated balanced realization techniques (ETBR) for large power grid analysis, the localized sensitivity-based decoupling capacitance allocation method, as well as a macro-model based sensitivity-based voltage drop noise reduction method, which was dominated as the Best Paper Award in 2009 IEEE/ACM Design Automation Conference. Fourth, we developed a host of statistical power grid noise analysis and interconnect delay computation techniques using the spectral stochastic method and variational subspace method to consider the unavoidable process variations and uncertainties during the manufacture process. The PI and his group at UCR have published intensively on the mentioned topic areas. We have published about 26 journal papers and 55 conference papers over the funding period. Many of the contributions have been published on the top-tied international conferences such as IEEE/ACM Design Automation Conference (DAC), IEEE International Conference on Computer-Aided Design (ICCAD), IEEE Asian Southern Pacific Design Automation Conference (ASPDAC), Design Automation and Test in Europe (DATE), and top journals such IEEE Transaction on CAD, IEEE Transaction on VLSI, IEEE transaction on Circuits and Systems etc. We also won one Best Paper Award from 2007 IEEE International Conference on Computer Design (ICCD’07) and one Best Paper Award Nomination from 2009 IEEE/ACM Design Automation Conference. In addition, we also published two monograph books to summarize the obtained research results for fast and broad dissemination of the research results and better graduate student training. Sheldon X.-D. Tan and Lei He, Advanced Model Order Reduction Techniques for VLSI Designs, Cambridge University Press, 2007, ISBN-13 978-0-521-86581-4, ISBN-10 0-521-86581. Ruijing Shen, Sheldon X.-D. Tan and Hao Yu, Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs, Springer, March 2012, ISBN-10: 1461407877. We also developed two software packages to share some of outcomes with the research communities: UiMOR – UC Riverside Model Order Reduction Tool Suite. UiMOR is a new stand-along circuit complexity reduction tool. It can perform reduction accurate for wideband frequency range with negligible loss of accuracy and is well suitable for analog/mixed-signal/memory designs. It also works well for traditional delay and noise calculations in digital circuits as well. www.ee.ucr.edu/~stan/project/uimor/uimor_main.htm ETBD -- Extended Truncated Balanced Realization (EBTR) power grid solver. ETBR can perform parallel analysis on multi-core machines (based POSIX pthreads), for transient analysis of large on-chip power grid networks. It is very suitable for multi-core based parallel simulation of large power delivery networks in VLSI systems. www.ee.ucr.edu/~stan/project/pg_ana/pg_proj.htm On the education side, about 10 Ph.D. students received partial or full funding from this project. Among them, Dr. Jeffrey Fan became a tenure-track assistant professor at Florida International University. Dr. Hai Wang became an associate professor at University of Electronic Science and Technology of China (UESTC), Dr. Wei Wu is a research scientist at Intel Research Lab. Dr. Boyuan Yan is a post-doc at Texas A&M University. The REU supplementary funding also supported more then 10 undergraduate students. Among them, Amalia Aviles and Jaquline Garay are the Latino and female students, Kenneth Anguka is an American African student.
