The project examines probabilistic design methodologies for computer architectures based on Markov random fields (MRF). The MRF approach can model arbitrary digital circuits with logic operation arising from the interaction of neighboring circuit nodes. The computation proceeds via probabilistic propagation of states through the circuit, with inputs and outputs treated on an equal footing. This approach may be particularly appropriate when dealing with the nanoscale since they are susceptible to high levels of noise. The MRF logic can be implemented in modified CMOS-based circuitry that uses output-input feedback to maximize the joint probability of correct logic states, trading off circuit area and speed for crucial fault tolerance and noise immunity. The research will map a probabilistic MRF design methodology onto CMOS, proceeding from individual devices and small combinational and sequential logic test circuits, through to higher-level architectural designs.
High-end computing architectures will increasingly have to deal with issues of reliability and robustness, in the face of reduced noise margins, process variability, and manufacturing tolerances. The probabilistic design methodology being followed in this project investigates one direction to extend silicon digital logic beyond the limits imposed on standard designs by fundamental physical constraints.
