This research explores the application of optical technology to the communication problems of future high-performance computing (HPC) systems. The goal is to develop flexible and dynamically reconfigurable optical interconnection architectures that will scale to a large number of processors while delivering scalable bandwidth, low communication latency, low power consumption, and low cost. The proposed approach is an organized effort combining architecture, technology, simulation and physical demonstration. The proposed research consists of three inter-related tasks: (1) Development and design of reconfigurable and scalable optical interconnection architectures for HPCs, (2) Identification and characterization of possible optical components necessary for the implementation of the proposed architectures, and (3) Development of analytic modeling and simulation tools for the precise physical modeling of the optical implementation techniques, as well as end-to-end system modeling of the proposed architectures.
As feature sizes in CMOS chips decrease to the sub-micron regime, and clock rates increase to the multi-GHz range, electrical interconnects are predicted to reach their fundamental limits and become the ultimate bottleneck for performance. This limitation will result in major bandwidth imbalances in future high-performance computers, and significantly affect their performance and scalability. One of the technologies that has been recognized to have the potential to solve communication problems of HPC systems is optical interconnects.
