Integrating digital logic, flash memory, analog, and RF blocks on a single integrated circuit (IC) chip to meet the high demands of todays small and low-cost consumer products has become increasingly difficult. Todays System-in-Package (SiP) technology involves the system integration of multiple semiconductor dies from various technologies into a common package. This high-density system integration is made possible through interconnections between active devices, such as IC chips or between other discrete components, mounted on the package substrate. High resolution testing for todays SiP is becoming increasingly difficult due to the ultra fine geometry associated with the nano-scale wafer level packaging. The goal of this research is to explore a new and low-cost test technique for detecting interconnect defects in nano-scale SiP substrates. We propose to (1) develop the nano-scale interconnect modeling, (2) establish look-up table database, (3) fabricate an integrated MEMS probe that incorporates a MEMS resonator, and (4) implement embedded system integration for practical demonstration. The overall program ties research and education at all levels (K-12, undergraduate, graduate, continuing-education). Through the Multicultural Engineering Program (MEP), we are planning to facilitate recruitment, retention and graduation of minority engineering students by providing participation and education in nanoelectronics testing areas. We plan to develop Internet-based modules on nano-scale packaging and testing.
