Modern Integrated Circuits (ICs) are built of elements so small that some of them may be too small to be fabricated correctly on everyone fabricated device. Art of modern IC manufacturing is in choosing such scale of miniaturization IC elements (typically transistors) that pushes available technology to its limits, i,e, to the stage in which number of fabricated ICs that work correctly is acceptable and at the same time the number of elements in a single IC as large as possible (by making them as small as possible).
To achieve such a balance one must understand specific circumstances causing IC malfunction. Typically such knowledge is acquired by using special purpose test structures, which are fabricated instead of normal IC and therefore are wasting very expensive manufacturing capacity.
The key idea of the research covered by this project is in the use of IC products themselves for calibration of manufacturing yield models. These models form a foundation of methodologies used for assessment probability of IC malfunctions.
