As scaling of CMOS devices continues unabated beyond the 90 nm node, a number of critical challenges including severe short-channel effects, increasing leakage currents and power dissipation are accelerating the introduction of new materials and device structures to extend the lifetime of CMOS down to, and perhaps beyond the 22 nm node. These devices are classified as non-classical CMOS and include strained-Si, ultra-thin body Silicon-on-Insulator (UTB-SOI), double-gate (such as FinFETs) and multi-gate devices. While these device structures seek to address the above mentioned scaling challenges, thermal management in these ultra scaled devices is an increasing concern made worse by the introduction of materials with poorer thermal conductivity (SOI, SiGe) and the physical confinement of the device geometries. Moreover, for device geometries where the mean free path of the phonons are comparable to (or larger than) the device size (channel length), classical drift-diffusion theory fails to accurately predict the temperature profile in the channel region of the transistors. At present, CAD tools that are widely used for device level electrothermal simulations, use drift-diffusion or hydrodynamic models and energy-balance equations assuming local thermodynamic equilibrium and therefore do not account for these effects, thereby compromising the performance and reliability of integrated circuits based on these devices. Moreover, there is no well defined methodology that combines electrothermal models at different length scales (as needed for a CMOS transistor) and subsequently generates accurate compact models to allow fast electrothermal simulations. Additionally, lack of thermal management in these emerging CMOS devices can also lead to significant increase in reliability problems such as electrostatic discharge (ESD), which is known to be the largest single cause of all IC failures in the semiconductor industry. Hence, there is an imminent need for developing suitable CAD framework for accurate multi-scale electrothermal modeling and simulation, in order to understand the impact of thermal effects on the electrical characteristics of these non-classical devices and subsequently on their circuit performance and reliability. The framework is also critical for optimizing the design of these devices and to understand various electrical-thermal tradeoffs. The PI plans to develop the necessary CAD framework to enable multi-scale electrothermal modeling and simulation capabilities for ultra-scaled non-classical CMOS devices. The research involves a unique approach that combines a small-scale sub-continuum electrothermal simulation methodology involving the electron-phonon Boltzmann Transport Equations (BTE) with a macro-scale heat-diffusion based methodology. The small-scale simulations are necessary to account for the non-locality of phonon transport near the high electric field (drain) region of the transistor and involve self-consistent solutions of the electron-BTE and the phonon-BTE to generate accurate heat flux and thermal profile along the channel of the device. Next, by coupling together the results of these simulations with the ones from classical heat-diffusion approach (for other areas of the transistors) the PI will develop accurate physical as well as compact models for various electrothermal quantities including thermal resistance, thermal capacitance and thermal time constant as a function of device materials, process and bias conditions, and device geometry. These compact models will then be used to carry out fast steady-state and transient electrothermal simulations using SPICE and thereby analyze and optimize various transistor architectures. Most importantly, since performance and power dissipation are critically dependent on the thermal profile, the electrothermal CAD framework will be used to design thermally-aware circuits so that maximum benefit can be derived from them and various electrical-thermal tradeoffs can be carried out. Additionally, the PI will study implications for ESD protection circuitsunderstand electrothermal behavior under high-current conditions and optimize device design for improving ESD reliability. The overall program also ties research to education at all levels (K-12, undergraduate, graduate, continuing-ed) partly via participation in programs designed by education professionals. As an affiliated faculty of the California NanoSystems Institute (CNSI), the PI plans to participate in various outreach activities sponsored by the CNSI as well as those offered by the Materials Research Lab (MRL) and the Nanotech (NNIN) at UCSB including the student and teacher research training internship programs. Additionally, the project provides a substantial focus on recruitment and retention of underrepresented groups into nanoscience and engineering.
