With the advance of the VLSI technology, the variation of interconnect delay is becoming critical since interconnect delay plays a dominant role in system performance. Process, voltage, and temperature variations can have significant effects on interconnect delay. Therefore, the robustness of interconnect design is important. This is especially crucial for clock distributions because the delay variations contribute to clock jitters and skews. In a recent invention, Cheng's group devised a distortionless transmission line which achieves the speed of light at an 85% or greater reduction in power consumption over traditional wires. The proposed project explores the utilization of the distortionless transmission line integrated with the interconnect topologies, circuit styles, and electromagnetic wave techniques into a hybrid network. The exploration can lead to the design of the speed of light, extremely low power, and low jitter clock distributions. The SGER is the best means for this exploratory and high return project because of the availability of the funding in a timely manner.
