The evolution of semiconductor technology and computer systems has made interconnection networks, and particularly on-chip interconnection networks (OCNs), a critical technology. In recent years, single-processor performance has reached a plateau, leading processor manufacturers to combine many processors on a chip. Such multi-core or many-core chip multi-processor (CMP) architectures depend on an OCN to provide communication between processors, cache memory modules, and external memories and I/O devices. A large fraction of area and power in such systems is consumed by communication making OCNs even more critical.
The PIs propose to develop enabling technology (circuits and architecture) for OCNs. They will develop circuits that are expected to reduce OCN power by 10x and decrease cost by 4x for an OCN with constant performance. This circuit-level work will enable the development of accurate models for the cost, power, and performance for key OCN components. Using these models, new network architectures will be developed that are expected to close much of the gap between an OCN and the ideal interconnect to 1/3 of its present size. The technology developed will be demonstrated through implementing an optimized OCN to the level of completed layout. While the OCN will be targeted for CMPs and driven by CMP workloads through the RAMP infrastructure, the PIs will also be working with systems-on-chip groups to inject the proposed circuit macros and architectural designs into their design tool-chains.
