This project investigates multicore architectures, advanced design tools, and highly-parallel applications to exploit three-dimensional integrated circuits (3D ICs) for significantly higher performance and reduced power, compared to traditional two-dimensional multicore chips. The goal is to exploit and extend both dimensions into the next computational frontier: trillion Operations-per-Second (TeraOPS) performance with less than 10W of power dissipation. The project involves detailed tradeoff analyses of architectural alternatives, especially with respect to memory hierarchy and interconnection networks, in order to discover approaches that fully exploit the benefits of 3D integration. This analysis will be performed at both the architectural level and the physical design level, and tools will be developed to allow information and constraints to smoothly flow between these levels of abstraction, enabling new opportunities for collaboration between architects and chip designers.
